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Contents:
  1. Bibliographic Information
  2. Publications and patents
  3. Product details
  4. High Mobility and Quantum Well Transistors

Om boka. Ta kontakt med Kundesenteret. Avbryt Send e-post. However, mere transistor downsizing does no longer provide the same improvements.

Inventor or coinventor of over 90 patents. Invited speaker at numerous international conferences and Workshops. This included the characterization of their magnetotransport, electrical, optical and structural properties, fabrication of various semiconductor devices, and epitaxial growth of strain tuning platforms and novel low-dimensional semiconductor structures. Some results of his research are given in 38 published articles in refereed international scientific journals and 72 abstracts and articles included in international conference books and proceedings.

Lecture: Advanced global strain-tuning platforms.

Issues relating to the growth, characterization and applicability of global strain-tuning platforms in future CMOS technologies will be considered. Although processed-induced strain is being used extensively by the silicon industry, global platforms can be used to induce relatively high values of strain for at least development work, and are especially useful when new channel materials SiGe, Ge are been investigated. Both biaxial and uniaxial strain tensions can be produced in global platforms, the latter involving patterning the channel layers.

The mechanisms of strain relaxation in the Si-Ge material system will be presented, with possible approaches to managing these processes for global platform creation and production.

Related Material other than Publications and Awards

The talk will look at different ways of growing the global platforms including considering the attributes of MBE and CVD growth techniques for producing very thin structures which can give very smooth platform surfaces and thicker structures which can yield low defect levels.

New designs are being considered that might enable dramatic improvements in the quality of platforms. Finally, the realization of CMOS compatible global platforms will be considered including economic aspects and potential application in the creation of strained Si and Ge on insulator platforms. He is author or co-author of more than scientific articles. Skotnicki holds about 50 patents on new devices, circuit and technologies.

He has presented over 50 Invited Papers and Short Course Lectures, co- authored about scientific papers review based , one book and several book chapters in the field of CMOS devices and circuits. From to , he was with the IBM T. Watson Research Center.

Bibliographic Information

He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronics systems. Novel devices often enable new concepts in circuit and system designs.

His research also includes explorations into circuits and systems that are device-driven. His present research covers a broad range of topics including carbon nanotubes, semiconductor nanowires, self-assembly, exploratory logic devices, and novel memory devices. Lecture: Emerging Memories.

Semiconductor-free microelectronics

Yet, recent advances in new materials, device technologies and circuits have made many emerging memories attractive candidates for a new generation of memories. These new generations of memories promise better or a different set of read, write, endurance, and retention characteristics from the conventional memories. It is also possible to contemplate new system design scenarios based on these new memory characteristics.


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In addition, the technology for integrating these new memories may permit three-dimensional stacking, integration of memory with CMOS logic on the same chip, or introduction of memory in new application areas such as embedded processors or dynamically reconfigurable logic.

In this talk, we will give an overview of the various emerging memories followed by a discussion on future scaling scenarios. Jimmy Xu is the Charles C. He received several prizes and awards including the Steacie Prize of Canada, was made a Guggenheim Fellow in , and was a finalist in for the Thatcher H.

Monday 30th june.

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Publications and patents

Tuesday 1st July. Wednesday 2nd July. Lecture 3: Advanced global strain-tuning platforms M. Lecture 7: Low Schottky barrier source-drain contacts E. Lecture Emerging Nanotechnologies T. Lecture 2: Silicon-On-Nothing nanodevices T. Lecture 4: Small Slope Switches A.

Lecture 5: High-K dielectrics and metal gates O. Lecture Nanowires J. Gala Dinner in Grenoble. Break fast. Welcome and registration.

Product details

Baldi M. Goldbach T. Baron A. Ionescu A. Dimoulas C. Dubois M. Myronov G. Eneman J. Raskin O. Engstrom T. Skotnicki T. Ernst H-S Ph. Wong G. Ghibaudo J. Nguyen and I. Cayrefourcq In this lecture, will be presented SOI materialsStrained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a performance gain from one technology node to the next. Uniaxial strained silicon has already made its way into IC manufacturing since the 90nm node.

High Mobility and Quantum Well Transistors

At the substrate level, strained silicon on insulator is a major innovation that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. This review focuses on the development of strained silicon, its impact on device properties and its scalability beyond 32nm design rules.

Lecture: Nanowires. Gate-All-Around nanowires are foreseen as a promising candidate for reducing the short channel effects of MOSFET beyond node 22 nm and tend to the so-called 1-D devices. Most of these issues will be addressed during the lecture. Lecture: Silicon-On-Nothing nanodevices. These changes are understandable when realizing that the modern CMOS circuits contain in the order of one billion of transistors on-chip! Smaller and more rapid devices are still required, but only on condition they are manufacturable in billions of identical parts within a chip, otherwise even the most rapid nano-devices are just useless.

The Silicon-On-Nothing SON technology is capable to fabricate mono-crystalline Silicon membranes with a nanometer thickness and an atomic precision. We will show how to integrate this kind of membranes into the conventional Bulk CMOS process to end up with extremely reproducible and well controlled nanotransistors. The SON technology helps to remove many CMOS limitations in terms of performance, electrostatic integrity, and power dissipation remaining perfectly controllable and scalable into the singular nanometers realm. Thereby we will conclude with a positive message, saying that at no level nor device, neither circuit nor system CMOS is running out of steam.

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